1. Field of the Invention
The present invention relates to a serial data transfer apparatus for converting parallel data into serial data for transmitting/receiving, and more particularly, to a control in setting/resetting a receiving permission bit thereof.
2. Description of the Related Art
Conventional data transfer apparatus starts its receiving operation when a receiving permission bit is set, and completes its receiving operation when a receiving permission bit is reset.
As an example of such conventional data transfer apparatus, a serial data transfer function included in the M37720 which is a single-chip microcomputer manufactured by Mitsubishi Electric Corporation will be explained on the basis of "Mitsubishi One-Chip Microcomputer User's Manual (July, 1991)".
FIG. 1 is a block diagram showing a configuration of the above-mentioned single-chip microcomputer M37720.
In FIG. 1, reference numeral 701 designates an odd side of data bus; numeral 702, an even side of the data bus; numeral 703, a receiving buffer register; and numeral 704, a receiving register.
The receiving register 704, which is connected to a receiving terminal RxDi, takes in received data in synchronism with a receiving clock given from a receiving control register 707 and gives the data to the receiving buffer register 703. The receiving buffer register 703, which is connected to the data buses 701 and 702, outputs the received data to them.
Reference numeral 705 designates a transmit register; numeral 706, a transmit buffer register; numeral 707, a receiving control register; numeral 708, a transmit control circuit; numeral 709, a 16-frequency dividing circuit; numeral 710, a 2-frequency dividing circuit; and numeral 711, a baud rate generator.
The transmit buffer register 706, which is connected with the data buses 701 and 702, holds the transmit data given from the data buses 701 and 702. The transmit register 705, to which a transmit clock is given from the transmit control circuit 708, reads the transmit data held by the transmit buffer register 706 in synchronism with the transmit clock, and transmits the data from a transmit terminal TxDi to the outside.
The baud rate generator 711 and frequency dividing circuits 709, 710 are used to set a baud rate in transferring data, in other words, to set the frequency of the transmitting/receiving clock.
FIG. 2 is a schematic diagram showing the function of a transmitting/receiving register 800.
The transmitting/receiving register 800 consists of 8 bits, b7 through b0.
In FIG. 2, reference numeral 801 designates an errorsome flag; numeral 802, a parity error flag; numeral 803, a framing error flag; numeral 804, an overrun error flag; numeral 805, a receiving completion flag; numeral 806, a receiving permission bit; numeral 807, a transmit buffer empty flag; and numeral 808, a transmit permission bit.
The errorsome flag 801 represents the presence/absence of error; the parity error flag 802, the presence/absence of parity error; the framing error flag 803, the presence/absence of framing error; the overrun error flag 804, the presence/absence of overrun error; the receiving completion flag 805, the presence/absence of the receive data in the receiving buffer register 703; the receiving permission bit 806, the inhibition/permission of receiving; the transmit buffer empty flag 807, the presence/absence of the transmit data in the transmit buffer register 706; and the transmit permission bit 808, the inhibition/permission of transmit.
The bits 801 through 808 of the transmitting/receiving register 800 are set/reset in the described manner. However, in resetting the transmitting/receiving register 800, all 8 bits are simultaneously reset to "0".
FIG. 3 is a schematic diagram showing a function of a transmitting/receiving mode register 900 of the block diagram also shown in FIG. 1.
The transmitting/receiving mode register 900 consists of 8 bits, b7 through b0.
In FIG. 3, reference numeral 901 designates a sleep select bit; numeral 902, a parity permission bit; numeral 903, a parity odd/even select bit; numeral 904, a stop bit length select bit; numeral 905, an internal/external clock select bit; and numerals 906 through 908, serial I/O mode select bits.
The sleep select bit 901 sets the invalid/valid of sleep function; the parity permission bit 902, the inhibition/permission of parity; the parity odd/even select bit 903, the odd number/even number of parity; the stop bit length select bit 904, 1 bit/2 bits of stop bit; the internal/external clock select bit 905, internal clock/external clock; and the serial I/O mode select bits 906 through 908 set serial I/O modes.
With reference to a timing chart of FIG. 4 showing an operating state, the receiving operation of the conventional data transfer apparatus as described above will be explained hereinafter.
At first, before the apparatus starts receiving, each bit of the transmitting/receiving mode register 900 is set by the CPU not shown. Specifically, performed are the internal/external clock selection of reference clock, stop bit length selection, parity odd/even selection, parity permission, and sleep selection. A positive integer value "n" is set to the baud rate generator 711.
Then, when the transmit permission bit 808 of the transmitting/receiving register 800 is set, the input of transfer data becomes possible, so that when a start bit is inputted from the receiving terminal RxDi, receiving is started. Subsequently the receive data RxD, and finally the stop bit are inputted.
When the stop bit is inputted, the completion of the receive data is detected, thereby causing the receiving completion flag 805 of the transmitting/receiving register 800 to be set.
Where upon the completion of receive, parity error, framing error, or overrun error is detected, the parity error flag 802, the framing error flag 803, or the overrun error flag 804 are set, respectively. Further, where either off those errors occurs, the errorsome flag 801 is set.
Now, in the serial data transfer function of the single-chip microcomputer M37720 as an example of conventional data transfer apparatus as described above, at the same time when the receiving permission bit 806 of the transmitting/receiving register 800 is reset to "0", the receiving completion flag 805, the parity error flag 802, the framing error flag 803 and the overrun error flag 804 are also cleared to "0". This procedure is shown in the timing chart of FIG. 4.
In the conventional data transfer apparatus as described above, a problem has existed in that where the receiving permission bit 806 is reset to "0" before the receiving completion flag 805, the parity error flag 802, the framing error flag 803 and the overrun error flag 804 of the transmitting/receiving register 800 are read, all the above-mentioned flags are cleared to "0".
The present invention is made in view of such circumstances, and it is an object of the invention to provide a serial data transfer apparatus by which the resetting of the transmit permission or receiving permission bit can be performed independently of the clearing of the transmit or receiving status so that where the transmit permission or the receiving permission is disabled, the status flag of transmit or the status flag of receiving is not cleared.